In a semiconductor manufacturing process, an electric characteristic test such as a conductivity test is performed to detect a defective product by bringing probes having conductivity (conductive probes) into contact with a wafer before dicing (WLT: Wafer Level Test). When this WLT is performed, to transfer a signal for a test to the wafer, a probe card including a large number of probes is used. In the WLT, the probes are individually brought into contact with each of dies on the wafer while the dies are scanned by the probe card. However, because several hundreds to several ten thousands dies are formed on the wafer, it takes considerable time to test one wafer. Thus, an increase in the number of dies causes higher cost.
To solve the problems of the WLT, recently, a method called FWLT (Full Wafer Level Test) is also used in which several hundreds to several ten thousands probes are collectively brought into contact with all or at least a quarter to a half of dies on a wafer (for example, see Patent document 1). To accurately bring the probes into contact with electrode pads on the wafer, this method requires technologies for maintaining positional accuracy of tips of probes by accurately keeping the parallelism or the flatness of a probe card with respect to a surface of the wafer and for highly accurately aligning a wafer.
Patent document 1: Japanese translation No. 2001-524258 of PCT international application